XPP TECHNOLOGY

>   Software Defined Products

>   C-Based Design Flow

>   XPP-III Processor Core

>   Function PAE

>   XPP Array

SOFTWARE DEFINED PRODUCTS
Continuously evolving "standards" and increasing complexity are challenging manufacturers of next generation multi media devices. Only fully programmable hardware architectures allow to shorten design cycles and reduce costs.
The new XPP-III DSP architecture is C-progammable on all levels. It eliminates the need for hardware accellerators since it integrates both, a reconfigurable array and versatile processor cores with outstanding sequential performance.
The XPP-III provides
  • Software programmability on all levels while minimising the need for fixed hardwired accellerators
  • Processing performance and ample bandwidth for any HD video standard and audio
  • Headroom to implement additional software features and to adopt new "standards"
  • Software libraries for the key video applications and codecs
  • Sophisticated compiler and design tools
SOFTWARE DESIGN
A complete suite of compilers and development tools is available for design entry, software simulation and verification of code.

A layered software structure provides several abstraction levels for the application design. The DirectXPP APIs and drivers hide hardware implementation details from the programmer. The XPP elements can be progammed using the C-compilers which allow integration of Function PAE assembler routines and XPP-array configurations written in the native mapping language NML.

The simulation environment provides fast and cycle accurate simulation of the whole XPP-III architecture including default SoC components such as interrupt controllers, DMA and caches. Graphical debugging tools display the execution of code on all elements of the XPP-III.